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グローバルCOE国際シンポジウム

■ PROGRAM


Global COE International Symposium
“Silicon Nanodevices in 2030: Prospects by world’s leading scientists”
Sponsored by Global COE Program “Photonics Integration-Core Electronics”,
Quantum Nanoelectronics Research Center, and Frontier Research Center,
Tokyo Institute of Technology
Co-sponsored by IEEE EDS Japan Chapter
Technical-Cosponsored by IEEE Electron Device Society
in Cooperation with Silicon Technology Division, Japan Society for Applied Physics,
NEDO, and JST

■ Tuesday, 13 October

■Opening Session
10:00 Welcome Remark　K. Iga, (President, Tokyo Tech.)
10:10 Greetings from IEEE EDS　S. Kimura, (Vice Chair, IEEE EDS Japan Chapter/ Hitachi Ltd)
10:15 Silicon Nano-Devices; Physics and Usefulness.　T. Sugano (Professor Emeritus, Univ. Tokyo)
10:35 Special Lecture “My years at Bell Laboratories (1963-1989) ”.

S. M. Sze(Bell Lab, U.S.A. & National Chao Tung Univ., Taiwan)

11:35 Lunch Break

■Session 1
12:30 Miniaturization and future prospects of Si devices.　H. Iwai (Tokyo Tech.)
13:00 Physics for Si nanowire FET and its fabrication.　K. Shiraishi (Tsukuba Univ.)
13:30 Large-scale density-functional calculations for atomic and electronic structures of Si nanowires.

A. Oshiyama (Univ. Tokyo)
14:00 Simulation of Electron Transport in Si Nano Devices.　N. Sano(Tsukuba Univ.)
14:30 A Compact Modeling of Quasi-Ballistic Si Nanowire MOSFET.　K. Natori (Tokyo Tech.)

15:00 Break and Poster session

■Session 2
15:30 Effective mobility and backscattering coefficients in short gate-length nanowire FETs.
G. Baccarani (Univ. Bologna)
16:00 Prospects of Silicon Nano-Electronics with the Vertical Nano-Pillar Approaches, Their Challenges
and Solutions.　Dim-Lee Kwong (IME, Singapore)
16:30 NanoCMOS Scaling by the End of the Roadmap and Beyond featuring Thin Films, Nanowires and
Heterogeneous Integration on Silicon.　S. Deleonibus (LETI, France)
17:00 Fabrication of Si nanowire FET and observed high-drain conduction.　K. Yamada (Waseda Univ.)
17:30 Mobility and strain characteristics in silicon nanowire FETs.　T. Hiramoto (Univ. Tokyo)
18:00 Fabrication and Characterization of Si and Heterojunction Tunnel Field Effect Transistors.
C. Claeys (IMEC)

18:30 Reception at Royal Blue Hall

■ Wednesday, 14 October

■Session 3
9:45 New channel material MOSFETs on Si platform.　S. Takagi (Univ. Tokyo)
10:15 InGaAs/InP MISFET. Y. Miyamoto (Tokyo Tech.)
10:45 Theory of carbon nanotubes and graphenes.　T. Ando (Tokyo Tech.)
11:15 CNTs vs Si nanowires.　W.I. Milne (Cambridge Univ. U.K.)
11:45 Carbon based active and passive devices for next-generation ICs.
K. Banerjee (Univ. California at Santa Barbara, U.S.A.)

12:15 Lunch Break

■Session 4
13:15 Silicon quantum dots and related devices　S. Oda (Tokyo Tech.)
13:45 Application of Si nanocrystals.　N. Koshida (Tokyo Univ. Agri. & Tech.)
14:15 Quantum computing based on coupled Si quantum dots. D. Williams (Hitachi Cambrdige Lab. U.K.)
14:45 Spin-functional MOSFETs.　S. Sugahara (Tokyo Tech.)
15:15 Trends and prospects of Si devices for LSI applications.　K. Uchida(Tokyo Tech.)

15:45 Break and Poster session

16:30 Panel Discussion: Si nanodevices in 2030
18:30 Closing Remarks and Best Poster Awards Presentation　H. Ishiwara (Tokyo Tech.)
18:45 Wrap up