■ PREFACE

Continuous advances in the performance and chip complexity of integrated circuits according to the Moore's law based on the miniaturization of transistors over the past 50 years have enabled the Information Age for 21st century society. Today, however, the minimum feature size of transistors is in nanometer range and further scaling can be achieved not simply by miniaturization, but with introduction of new materials or strains in the film.

On the other hand, novel applications in logic, memory and sensor devices are proposed based on the fusion of CMOS technology with MEMS technology. Hybrid technology with new materials or variables (mechanical, photonic, spin, etc) is essential for future advance of CMOS technology.

The purpose of this international symposium is to bring together world's leading scientists in the field of silicon nanodevices and discuss about future directions of hybrid nanodevice technology.

This symposium is jointly organized by JSPS Global COE Program PICE and European FP7 Project NEMSIC, and IEEE EDS Japan Chapter.

Co-organizers: Shunri Oda (TIT), Hiroshi Iwai (TIT) and Adrian Ionescu (EPFL)